ARM: entry: rejig register allocation in exception entry handlers

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This allows us to avoid moving registers twice to work around the
clobbered registers when we add calls to trace_hardirqs_{on,off}.

Ensure that all SVC handlers return with SPSR in r5 for consistency.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Russell King 2011-06-25 15:44:20 +01:00

parent fbab1c8094

commit b059bdc393

1 changed files with 43 additions and 38 deletions

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arch/arm/kernel/entry-armv.S

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