perf, x86: Add Intel SandyBridge CPU support

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This patch adds basic SandyBridge support, including hardware
cache events and PEBS events support.

It has been tested on SandyBridge CPUs with perf stat and also
with PEBS based profiling - both work fine.

The patch does not affect other models.

v2 -> v3:
 - fix PEBS event 0xd0 with right umask combinations
 - move snb pebs constraint assignment to intel_pmu_init

v1 -> v2:
 - add more raw and PEBS events constraints
 - use offcore events for LLC-* cache events
 - remove the call to Nehalem workaround enable_all function

Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>
LKML-Reference: <1299072424.2175.24.camel@localhost>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

...

This commit is contained in:

Lin Ming 2011-03-02 21:27:04 +08:00 • committed by Ingo Molnar

parent a639dc64e5

commit b06b3d4969

3 changed files with 165 additions and 1 deletions

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4

arch/x86/kernel/cpu/perf_event.c

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124

arch/x86/kernel/cpu/perf_event_intel.c

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38

arch/x86/kernel/cpu/perf_event_intel_ds.c

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