net: axienet: Enable more clocks

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This driver was only enabling the first clock on the device, regardless
of its name. However, this controller logic can have multiple clocks
which should all be enabled. Add support for enabling additional clocks.
The clock names used are matching those used in the Xilinx version of this
driver as well as the Xilinx device tree generator, except for mgt_clk
which is not present there.

For backward compatibility, if no named clocks are present, the first
clock present is used for determining the MDIO bus clock divider.

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

...

This commit is contained in:

Robert Hancock 2021-03-25 18:04:38 -06:00 • committed by David S. Miller

parent a0e55dcd2f

commit b11bfb9a19

3 changed files with 35 additions and 11 deletions

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8

drivers/net/ethernet/xilinx/xilinx_axienet.h

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34

drivers/net/ethernet/xilinx/xilinx_axienet_main.c

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4

drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c

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