riscv: fix misaligned access handling of C.SWSP and C.SDSP

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[ Upstream commit 22e0eb0483 ]

This is a backport of a fix that was done in OpenSBI: ec0559eb315b
("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP").

Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
register, so checking that the rs2 field is non-zero is unnecessary.

Additionally, the previous check was incorrect since it was checking
the immediate field of the instruction instead of the rs2 field.

Fixes: 956d705dd2 ("riscv: Unaligned load/store handling for M_MODE")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231103090223.702340-1-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Clément Léger 2023-11-03 10:02:23 +01:00 • committed by Greg Kroah-Hartman

parent 92f095553a

commit b12ccda0d4

1 changed files with 2 additions and 4 deletions

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arch/riscv/kernel/traps_misaligned.c

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