x86, cacheinfo: Unify AMD L3 cache index disable checking

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All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3
cache index disable. Concentrate the family, model, stepping checking at
one place and enable the feature implicitly on upcoming Fam10h models.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

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Borislav Petkov 2010-04-22 16:06:58 +02:00 • committed by H. Peter Anvin

parent 6dad2a2964

commit b1ab1b4d9a

1 changed files with 10 additions and 7 deletions

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arch/x86/kernel/cpu/intel_cacheinfo.c

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