drm/i915/guc: Update guc shim control programming on newer platforms

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Starting from xehpsdv, bit 0 of the GuC shim control register has
been repurposed, while bit 2 is now reserved, so we need to avoid
setting those for their old meaning on newer platforms.

Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120222436.3449778-1-daniele.ceraolospurio@intel.com

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Daniele Ceraolo Spurio 2022-01-20 14:24:36 -08:00

parent db3b3f3e62

commit b229712b26

1 changed files with 5 additions and 3 deletions

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drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

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