drm/amd/display: Exit LS for ISHARP before coefficient write

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[Why]
The hardware programming guide indicates that we must exit LS before
any coefficient writes.

This is true across all ASIC for this block.

[How]
Drop the ips_v2 checks and unconditionall perform the update.
It is not based on IPS V2 support, which is set for DCN42, but rather
the presence of the block itself.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Nicholas Kazlauskas 2026-06-30 11:07:49 -04:00 • committed by Alex Deucher

parent 47c9c743ec

commit b23470a026

1 changed files with 11 additions and 14 deletions

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drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

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