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RISC-V updates for v7.3-rc7

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- Fix a regression in the Zbb-enabled strnlen() implementation when
   huge counts are specified
 
 - When userspace pointer masking is enabled, strip the tag from
   user-specified pointers in two spots in the RISC-V futex code where
   this was missing
 
 - When CONFIG_SHADOW_CALL_STACK=y, use a supervisor mode-only CSR bit
   to determine whether the trap came from userspace or not, rather
   than a userspace-writable register
 
 - Reset the HSTATUS.HU bit during CPU initialization to avoid
   unexpected behavior, as the RISC-V specification does not require
   this bit to be hardware-reset
 
 - Fix the T-Head GhostWrite probing code when !CONFIG_ERRATA_THEAD_MAE
 
 - Fix RV32 boots using 32-bit.config by constraining NR_CPUS
 
 - Implement a workaround for SiFive MAL-9092, which requires fences
   around hypervisor load/store instructions
 
 - Fix the RISC-V patch_map() code to work properly for EXECMEM
   addresses when !CONFIG_STRICT_MODULE_RWX
 
 - Fix ptrace register set access reporting when CFI landing pad or
   shadow stack support is enabled
 
 - Avoid copying garbage into the target's vstate when PTRACE_SETREGSET
   is called with a short iov_len
 
 - Fix load_unaligned_zeropad() on RV32 kernels with
   CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS=y
 
 - Fix build breakage for any userspace program that includes
   uapi/asm/vendor/mips.h
 
 - Fix a build warning for 32-bit allmodconfig builds related to SiFive
   errata
 
 - Fix misspecified inline assembly constraints in the vector context
   save/restore code
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Merge tag 'riscv-for-linus-7.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
 "Several security fixes, a significant strnlen() regression fix, and
  several other miscellaneous fixes:

   - Fix a regression in the Zbb-enabled strnlen() implementation when
     huge counts are specified

   - When userspace pointer masking is enabled, strip the tag from
     user-specified pointers in two spots in the RISC-V futex code where
     this was missing

   - When CONFIG_SHADOW_CALL_STACK=y, use a supervisor mode-only CSR bit
     to determine whether the trap came from userspace or not, rather
     than a userspace-writable register

   - Reset the HSTATUS.HU bit during CPU initialization to avoid
     unexpected behavior, as the RISC-V specification does not require
     this bit to be hardware-reset

   - Fix the T-Head GhostWrite probing code when
     !CONFIG_ERRATA_THEAD_MAE

   - Fix RV32 boots using 32-bit.config by constraining NR_CPUS

   - Implement a workaround for SiFive MAL-9092, which requires fences
     around hypervisor load/store instructions

   - Fix the RISC-V patch_map() code to work properly for EXECMEM
     addresses when !CONFIG_STRICT_MODULE_RWX

   - Fix ptrace register set access reporting when CFI landing pad or
     shadow stack support is enabled

   - Avoid copying garbage into the target's vstate when
     PTRACE_SETREGSET is called with a short iov_len

   - Fix load_unaligned_zeropad() on RV32 kernels with
     CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS=y

   - Fix build breakage for any userspace program that includes
     uapi/asm/vendor/mips.h

   - Fix a build warning for 32-bit allmodconfig builds related to
     SiFive errata

   - Fix misspecified inline assembly constraints in the vector context
     save/restore code"

* tag 'riscv-for-linus-7.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: fix load_unaligned_zeropad() fixup for RV32
  riscv: entry: gate shadow call stack reload on sstatus.SPP, not tp
  riscv: ptrace: Zero-initialize regset buffers before copyin
  riscv: ptrace: reject CFI regset access when extensions are absent
  riscv: fix NR_CPUS range leaking 64-bit default onto 32-bit builds
  riscv: errata: select RISCV_ALTERNATIVE_EARLY for THEAD GHOSTWRITE
  riscv: futex: untag the user pointer before the atomic access
  riscv: lib: Fix ZBB strnlen wrap-around regression on huge counts
  riscv: patch: fix handling of bpf-jit execmem addresses
  RISC-V: Clear HSTATUS.HU on CPU initialization
  RISC-V: errata: Add SiFive MAL-9092 workaround
  riscv: vector: Fix output operands in context save
  riscv: vector: Fix data pointer constraints in context save/restore
  riscv: limit sifive errata to CONFIG_64BIT
  riscv: hwprobe: use _BITULL() rather than BIT() in MIPS vendor uapi header
This commit is contained in:
Linus Torvalds 2026-10-11 08:13:52 -07:00
commit b2d929a1c2
20 changed files with 127 additions and 22 deletions
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