arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588

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VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.

The HDMI1 PHY PLL clock source cannot be added directly to vop node in
rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
optional feature and its PHY node belongs to a separate (extra) DT file.

Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
clocks & clock-names properties in the extra DT file.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Cristian Ciocaltea 2025-02-23 11:31:40 +02:00 • committed by Heiko Stuebner

parent aadaa27956

commit b2e668a60e

1 changed files with 21 additions and 0 deletions

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arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi

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