gpio: aspeed: Support G7 Aspeed gpio controller

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In the 7th generation of the SoC from Aspeed, the control logic of the
GPIO controller has been updated to support per-pin control. Each pin now
has its own 32-bit register, allowing for individual control of the pin's
value, direction, interrupt type, and other settings. The permission for
coprocessor access is supported by the hardware but hasn't been
implemented in the current patch.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20241008081450.1490955-8-billy_tsai@aspeedtech.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

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Billy Tsai 2024-10-08 16:14:50 +08:00 • committed by Bartosz Golaszewski

parent bef6959a37

commit b2e861bd1e

1 changed files with 147 additions and 0 deletions

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drivers/gpio/gpio-aspeed.c

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