drm/i915: ILK cdclk seems to be 450MHz

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Based on the BIOS DP A AUX 2x clock divider the cdclk frequency
on ILK is 450Mhz. At least that holds on my ILK and it matches
how we program the divider.

Supposedly cdclk is 400MHz on SNB and IVB, again based on the AUX 2x
clock divider. Note that I don't have a SNB or IVB machine with
eDP so I couldn't verify what the BIOS used, so this notion is
purely based on our current code,

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Ville Syrjälä 2015-03-31 14:11:54 +03:00 • committed by Daniel Vetter

parent e907f1704c

commit b37a6434cf

1 changed files with 8 additions and 0 deletions

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drivers/gpu/drm/i915/intel_display.c

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