clk: mediatek: Fix PLL registers setting flow

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Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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James Liao 2015-07-10 16:39:32 +08:00 • committed by Stephen Boyd

parent 9783c0d985

commit b3be457e58

1 changed files with 12 additions and 9 deletions

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drivers/clk/mediatek/clk-pll.c

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