clk: tegra: dfll: CVB calculation alignment with the regulator

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The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

...

This commit is contained in:

Joseph Lo 2019-01-04 11:06:48 +08:00 • committed by Thierry Reding

parent b0dcfb78dc

commit b3cf8d0695

4 changed files with 59 additions and 14 deletions

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6

drivers/clk/tegra/clk-dfll.h

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49

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

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12

drivers/clk/tegra/cvb.c

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6

drivers/clk/tegra/cvb.h

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