drm/i915: BDW clock change support

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Add support for changing cdclk frequency during runtime on BDW.

Also with IPS enabled the actual pixel rate mustn't exceed 95% of cdclk,
so take that into account when computing the max pixel rate.

v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
v4: Rebased to the latest
v5: Rebased to the latest
v6: Patch order shuffle so that Broadwell CD clock change is
    applied before the patch for Haswell CD clock change
v7: Fix for patch style problems

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

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This commit is contained in:

Ville Syrjälä 2015-06-03 15:45:13 +03:00 • committed by Jani Nikula

parent ebb72aad41

commit b432e5cfd5

2 changed files with 208 additions and 10 deletions

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2

drivers/gpu/drm/i915/i915_reg.h

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216

drivers/gpu/drm/i915/intel_display.c

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