arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s

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The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
instead of 1.1 GHz. Fix it.

Fixes: c9211fa260 ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Reported-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Cristian Ciocaltea 2023-04-02 12:50:51 +03:00 • committed by Heiko Stuebner

parent 87810bda8a

commit b46a22dea7

1 changed files with 1 additions and 1 deletions

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arch/arm64/boot/dts/rockchip/rk3588s.dtsi

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