ARM: dts: imx6q-b850v3: Update display clock source

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The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Akshay Bhat 2016-04-18 17:19:44 -04:00 • committed by Shawn Guo

parent 7532c98f3a

commit b492b8744d

1 changed files with 11 additions and 4 deletions

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arch/arm/boot/dts/imx6q-b850v3.dts

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