drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes

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[Description]
- Due to bandwidth / arbitration issues at 200Mhz DCFCLK,
  we want to enforce minimum 60us of prefetch to avoid
  intermittent underflow issues
- Since 60us prefetch is already enforced for UCLK DPM0,
  and many DCFCLK's > 200Mhz are mapped to UCLK DPM1, in
  theory there should not be any UCLK DPM regressions by
  enforcing greater prefetch

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Alvin Lee 2023-04-27 15:10:13 -04:00 • committed by Alex Deucher

parent f57fa0f23d

commit b504f99cca

2 changed files with 4 additions and 2 deletions

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5

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

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1

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h

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