drm/vc4: hvs: Fix frame count register readout

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In order to get the field currently being output, the driver has been
using the display FIFO frame count in the HVS, reading a 6-bit field at
the offset 12 in the DISPSTATx register.

While that field is indeed at that location for the FIFO 1 and 2, the
one for the FIFO0 is actually in the DISPSTAT1 register, at the offset
18.

Fixes: e538092cb1 ("drm/vc4: Enable precise vblank timestamping for interlaced modes.")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://lore.kernel.org/r/20220331143744.777652-3-maxime@cerno.tech

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This commit is contained in:

Maxime Ripard 2022-03-31 16:37:39 +02:00

parent 748acfc98a

commit b51cd7ad14

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4 changed files with 35 additions and 3 deletions

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2

drivers/gpu/drm/vc4/vc4_crtc.c

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1

drivers/gpu/drm/vc4/vc4_drv.h

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23

drivers/gpu/drm/vc4/vc4_hvs.c

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12

drivers/gpu/drm/vc4/vc4_regs.h

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