clk: qcom: ipq4019: correct sdcc frequency and parent name

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1. The parent for sdcc clock is sdccpll.
2. The frequency value was wrong so modified the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Abhishek Sahu 2016-11-25 21:11:31 +05:30 • committed by Stephen Boyd

parent 5c1a96935f

commit b52a0c2c11

1 changed files with 2 additions and 2 deletions

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drivers/clk/qcom/gcc-ipq4019.c

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