clk: tegra: pll: Adjust vco_min if SDM present

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This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.

Based on original work by Aleksandr Frid <afrid@nvidia.com>

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Bill Huang 2015-06-18 17:28:30 -04:00 • committed by Thierry Reding

parent 6929715cf6

commit b5512b45d5

2 changed files with 32 additions and 0 deletions

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28

drivers/clk/tegra/clk-pll.c

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4

drivers/clk/tegra/clk.h

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