drm/i915/cx0: Remove bus reset after every c10 transaction

Browse source

C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
transaction. Although not required by BSPEC bus resets were added for
prior platforms as a workaround. Starting with xe3_lpd this bus reset is
not necessary.

Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-6-clinton.a.taylor@intel.com

...

This commit is contained in:

Clint Taylor 2024-10-28 12:30:11 -07:00 • committed by Matt Roper

parent 55371ac670

commit b66a028a82

1 changed files with 4 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

6

drivers/gpu/drm/i915/display/intel_cx0_phy.c

View file