clk: renesas: r9a07g043: Add TSU clock and reset entry

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Add TSU clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2022-05-01 09:34:49 +01:00 • committed by Geert Uytterhoeven

parent 14d8857d82

commit b676853004

1 changed files with 6 additions and 0 deletions

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drivers/clk/renesas/r9a07g043-cpg.c

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