clk: meson: introduce new pll power-on sequence for A1 SoC family

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Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same.

In A1 PLL, the PLL enable sequence is different, so add new optional pll
reg bits and use the new power-on sequence to enable the PLL:
    1. enable the pll, delay for 10us
    2. enable the pll self-adaption current module, delay for 40us
    3. enable the lock detect module

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-3-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Dmitry Rokosov 2023-05-23 16:53:47 +03:00 • committed by Jerome Brunet

parent 02f1e17c41

commit b6ec400aa1

2 changed files with 25 additions and 0 deletions

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23

drivers/clk/meson/clk-pll.c

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2

drivers/clk/meson/clk-pll.h

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