drm/i915: IVB FBC WaFbcDisableDpfcClockGating

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Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: RMW to preserve other bits (by Ville)
v3: Fix from Ville: sed &/| at RMW
v4: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Rodrigo Vivi 2013-05-09 14:08:38 -03:00 • committed by Daniel Vetter

parent 30ca7c6f97

commit b74ea102b7

1 changed files with 11 additions and 0 deletions

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drivers/gpu/drm/i915/intel_pm.c

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