net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES

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The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline
size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Jisheng Zhang 2016-03-30 19:53:41 +08:00 • committed by David S. Miller

parent 13a7ebb38a

commit b7854efce2

1 changed files with 1 additions and 13 deletions

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14

drivers/net/ethernet/marvell/mvpp2.c

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