clk: rockchip: fix clock gate for rk3188 spdif_pre

Browse source

In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13.
This appears to be a copy-paste error because such a register does not exist.
We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock
is the same as the rk3066 spdif clock, so we move it to the common clock branches.

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

...

This commit is contained in:

Julien CHAUVEAU 2014-11-21 10:27:41 +01:00 • committed by Heiko Stuebner

parent f0c71718c2

commit b7bdb7f45e

1 changed files with 9 additions and 16 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

25

drivers/clk/rockchip/clk-rk3188.c

View file