clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2

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R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.

This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.

Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.

Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Geert Uytterhoeven 2017-03-29 17:22:44 +02:00

parent 2ea659a9ef

commit b7c563c489

1 changed files with 19 additions and 4 deletions

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drivers/clk/renesas/clk-rcar-gen2.c

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