clk: ingenic: jz4740: Fix gating of UDC clock

Browse source

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9c ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

This commit is contained in:

Paul Cercueil 2019-01-25 12:34:36 -03:00 • committed by Stephen Boyd

parent bfeffd1552

commit b7e29924a1

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

drivers/clk/ingenic/jz4740-cgu.c

View file