drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

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Using a heavy-weight TLB flush once is not sufficient. Concurrent
memory accesses in the same TLB cache line can re-populate TLB entries
from stale texture cache (TC) entries while the heavy-weight TLB
flush is in progress. To fix this race condition, perform another TLB
flush after the heavy-weight one, when TC is known to be clean.

Move the workaround into the low-level TLB flushing functions. This way
they apply to amdgpu as well, and KIQ-based TLB flush only needs to
synchronize once.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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This commit is contained in:

Felix Kuehling 2020-01-17 20:29:13 -05:00 • committed by Alex Deucher

parent 82c4ebfa35

commit b80cd524ac

2 changed files with 53 additions and 21 deletions

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6

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

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68

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

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