[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4

Browse source

OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.

linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

...

This commit is contained in:

Paul Walmsley 2009-01-28 12:08:14 -07:00 • committed by Russell King

parent f0587b63c2

commit b8168d1e39

1 changed files with 16 additions and 4 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

20

arch/arm/mach-omap2/clock34xx.h

View file