[Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel

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http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978

Section data_l1_cacheline_aligned should be defined in
link script of kernel, when L1 data sram bank A is not available.

In bf536 with all data cache is enabled, there is no L1 data sram.
Current link script won't define section data_l1.cacheline_aligned in
this case. But, if user select put cacheline_aligned data into l1 sram
in kernel menuconfig, these data will be dropped and access to these
data will trigger data CPLB exception.

Do panic in l1 relocation code as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

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This commit is contained in:

Sonic Zhang 2008-04-24 06:13:37 +08:00 • committed by Bryan Wu

parent 253bcf4f9b

commit b85b82d980

2 changed files with 8 additions and 3 deletions

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6

arch/blackfin/kernel/setup.c

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5

arch/blackfin/kernel/vmlinux.lds.S

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