clk: socfpga: Support multiple parents for the pll clocks

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The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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Dinh Nguyen 2014-02-19 15:11:11 -06:00 • committed by Mike Turquette

parent 5585f73175

commit b89cd950cb

1 changed files with 22 additions and 4 deletions

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drivers/clk/socfpga/clk-pll.c

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