ARCv2: barriers

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ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for
kernel proper.

SMP barrier is provided by DMB instruction which also guarantees local
barrier hence used as backend of smp_*mb() as well as *mb() APIs

Also hookup barriers into MMIO accessors to avoid ordering issues in IO

Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

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This commit is contained in:

Vineet Gupta 2015-03-11 21:42:37 +05:30

parent 470c27e469

commit b8a0330239

3 changed files with 87 additions and 4 deletions

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1

arch/arc/include/asm/Kbuild

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48

arch/arc/include/asm/barrier.h

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42

arch/arc/include/asm/io.h

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