ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl

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Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.

Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com>

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

...

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Gregory CLEMENT 2012-11-06 01:58:07 +01:00 • committed by Russell King

parent c3545236e8

commit b8db6b886a

3 changed files with 269 additions and 13 deletions

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4

arch/arm/include/asm/hardware/cache-l2x0.h

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55

arch/arm/mm/cache-aurora-l2.h

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223

arch/arm/mm/cache-l2x0.c

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