diff --git a/sound/soc/codecs/cx2072x.c b/sound/soc/codecs/cx2072x.c
index 83c6cbd40804..ffd6a5119f5e 100644
--- a/sound/soc/codecs/cx2072x.c
+++ b/sound/soc/codecs/cx2072x.c
@@ -96,51 +96,60 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_GPIO_WAKE, 0x00000000 },
 	{ CX2072X_GPIO_UM_ENABLE, 0x00000000 },
 	{ CX2072X_GPIO_STICKY_MASK, 0x00000000 },
-	{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
-	{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
-	{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
 	{ CX2072X_DAC1_POWER_STATE, 0x00000433 },
 	{ CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
 	{ CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
-	{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
-	{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
-	{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
+	{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
+	{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
+	{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
 	{ CX2072X_DAC2_POWER_STATE, 0x00000433 },
 	{ CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
-	{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
+	{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
+	{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
+	{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
 	{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
 	{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
 	{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
-	{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
-	{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
+	{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
 	{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
 	{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
 	{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
+	{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
+	{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
+	{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
+	{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
+	{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
+	{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
+	{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
 	{ CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
 	{ CX2072X_PORTA_POWER_STATE, 0x00000433 },
 	{ CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
 	{ CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
 	{ CX2072X_PORTA_PIN_SENSE, 0x00000000 },
 	{ CX2072X_PORTA_EAPD_BTL, 0x00000002 },
+	{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
+	{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
+	{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
 	{ CX2072X_PORTB_POWER_STATE, 0x00000433 },
 	{ CX2072X_PORTB_PIN_CTRL, 0x00000000 },
 	{ CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
@@ -148,43 +157,16 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_PORTB_EAPD_BTL, 0x00000002 },
 	{ CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
 	{ CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
-	{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
-	{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
 	{ CX2072X_PORTD_POWER_STATE, 0x00000433 },
 	{ CX2072X_PORTD_PIN_CTRL, 0x00000020 },
 	{ CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
 	{ CX2072X_PORTD_PIN_SENSE, 0x00000000 },
 	{ CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
 	{ CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
-	{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
-	{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
-	{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
-	{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
-	{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
-	{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
-	{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
-	{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
-	{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
-	{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
-	{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
-	{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
-	{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
-	{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
-	{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
-	{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
-	{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
-	{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
-	{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
-	{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
+	{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
+	{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
+	{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
 	{ CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
 	{ CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
 	{ CX2072X_SPKR_DRC_TEST, 0x00000000 },
@@ -195,12 +177,15 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_I2SPCM_CONTROL3, 0x00000000 },
 	{ CX2072X_I2SPCM_CONTROL4, 0x00000000 },
 	{ CX2072X_I2SPCM_CONTROL5, 0x00000000 },
-	{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
 	{ CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
+	{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
+	{ CX2072X_DIGITAL_TEST16, 0x00000021 },
+	{ CX2072X_DIGITAL_TEST17, 0x00000018 },
+	{ CX2072X_DIGITAL_TEST18, 0x00000024 },
+	{ CX2072X_DIGITAL_TEST19, 0x00000001 },
+	{ CX2072X_DIGITAL_TEST20, 0x00000002 },
 	{ CX2072X_CODEC_TEST2, 0x00000000 },
 	{ CX2072X_CODEC_TEST9, 0x00000004 },
-	{ CX2072X_CODEC_TEST20, 0x00000600 },
-	{ CX2072X_CODEC_TEST26, 0x00000208 },
 	{ CX2072X_ANALOG_TEST4, 0x00000000 },
 	{ CX2072X_ANALOG_TEST5, 0x00000000 },
 	{ CX2072X_ANALOG_TEST6, 0x0000059a },
@@ -215,11 +200,26 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_DIGITAL_TEST11, 0x00000000 },
 	{ CX2072X_DIGITAL_TEST12, 0x00000084 },
 	{ CX2072X_DIGITAL_TEST15, 0x00000077 },
-	{ CX2072X_DIGITAL_TEST16, 0x00000021 },
-	{ CX2072X_DIGITAL_TEST17, 0x00000018 },
-	{ CX2072X_DIGITAL_TEST18, 0x00000024 },
-	{ CX2072X_DIGITAL_TEST19, 0x00000001 },
-	{ CX2072X_DIGITAL_TEST20, 0x00000002 },
+	{ CX2072X_CODEC_TEST20, 0x00000600 },
+	{ CX2072X_CODEC_TEST26, 0x00000208 },
+	{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
+	{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
+	{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
+	{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
+	{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
+	{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
+	{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
+	{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
+	{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
+	{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
+	{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
+	{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
+	{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
+	{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
+	{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
 };
 
 /*