RISC-V: remove timer leftovers

This code is currently unused and will be added back later in a different
place with the real interrupt and clocksource support.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Christoph Hellwig 2018-08-04 10:23:12 +02:00 • committed by Palmer Dabbelt
commit b9490350f7
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