ASoC: cs42l42: Add PLL configuration for 44.1kHz/16-bit

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44.1kHz 16-bit standard I2S gives a SCLK of 1.4112 MHz. Add
a PLL configuration for this.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210805161111.10410-5-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Richard Fitzgerald 2021-08-05 17:11:08 +01:00 • committed by Mark Brown

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sound/soc/codecs/cs42l42.c

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