KVM: nVMX: Make nested control MSRs per-cpu

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To enable nested apicv support, we need per-cpu vmx
control MSRs:
  1. If in-kernel irqchip is enabled, we can enable nested
     posted interrupt, we should set posted intr bit in
     the nested_vmx_pinbased_ctls_high.
  2. If in-kernel irqchip is disabled, we can not enable
     nested posted interrupt, the posted intr bit
     in the nested_vmx_pinbased_ctls_high will be cleared.

Since there would be different settings about in-kernel
irqchip between VMs, different nested control MSRs
are needed.

Signed-off-by: Wincy Van <fanwenyi0529@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Wincy Van 2015-02-03 23:56:30 +08:00 • committed by Paolo Bonzini

parent f2b93280ed

commit b9c237bb1d

1 changed files with 129 additions and 86 deletions

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arch/x86/kvm/vmx.c

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