OMAP3: hwmod data: Fix incorrect SmartReflex -> L4 CORE interconnect links

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Commit d344272671 ("OMAP3: PM: Adding
smartreflex hwmod data") added data that claims that the L4 CORE has
two slave interfaces that originate from the SmartReflex modules,
omap3_l4_core__sr1 and omap3_l4_core__sr2.  But as those two data
structure records show, it's L4 CORE that has a master port towards
SR1 and SR2.
Move the incorrect data from slaves list to master list.

Based on a path by Paul Walmsley <paul@pwsan.com>

    https://patchwork.kernel.org/patch/623171/

That is based on a patch by Benoît Cousson <b-cousson@ti.com>:

    https://patchwork.kernel.org/patch/590561/

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoît Cousson <b-cousson@ti.com>
Cc: Sanjeev Premi <premi@ti.com>
Cc: Thara Gopinath <thara@ti.com>

...

This commit is contained in:

Benoit Cousson 2011-03-10 10:53:15 +01:00

parent 0dde52a9f5

commit b9ccf8afe2

1 changed files with 2 additions and 2 deletions

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arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

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