clk: keystone: add Keystone PLL clock driver

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Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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Santosh Shilimkar 2013-09-25 21:18:13 -04:00 • committed by Mike Turquette

parent 938cc3a14c

commit b9e0d40c0d

2 changed files with 389 additions and 0 deletions

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84

Documentation/devicetree/bindings/clock/keystone-pll.txt

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305

drivers/clk/keystone/pll.c

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