x86, MCE, AMD: Use MCG_CAP MSR to find out number of banks on AMD

Browse source

Currently number of error reporting register banks is hardcoded to
6 on AMD processors. This may break in virtualized scenarios when
a hypervisor prefers to report fewer banks than what the physical
HW provides.

Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0]
that's what we should use.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Link: http://lkml.kernel.org/r/1363295441-1859-3-git-send-email-boris.ostrovsky@oracle.com
[ reverse NULL ptr test logic ]
Signed-off-by: Borislav Petkov <bp@suse.de>

...

This commit is contained in:

Boris Ostrovsky 2013-03-14 17:10:41 -04:00 • committed by Borislav Petkov

parent c76e81643c

commit bafcdd3b6c

1 changed files with 15 additions and 7 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

22

arch/x86/kernel/cpu/mcheck/mce_amd.c

View file