clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

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The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.

Add CLK_SET_RATE_PARENT flag to this clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Icenowy Zheng 2016-12-13 23:22:48 +08:00 • committed by Maxime Ripard

parent 790d929b54

commit bb021cda2c

1 changed files with 1 additions and 1 deletions

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drivers/clk/sunxi-ng/ccu-sun8i-a33.c

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