KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT

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Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR.  KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Sean Christopherson 2020-03-02 18:02:36 -08:00 • committed by Paolo Bonzini

parent 8053f924ca

commit bb1fcc70d9

5 changed files with 37 additions and 12 deletions

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12

arch/x86/include/asm/vmx.h

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11

arch/x86/kvm/mmu/mmu.c

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2

arch/x86/kvm/mmu/paging_tmpl.h

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21

arch/x86/kvm/vmx/nested.c

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3

arch/x86/kvm/vmx/vmx.c

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