x86/platform/uv: Update TSC sync state for UV5

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The UV5 platform synchronizes the TSCs among all chassis, and will not
proceed to OS boot without achieving synchronization.  Previous UV
platforms provided a register indicating successful synchronization.
This is no longer available on UV5.  On this platform TSC_ADJUST
should not be reset by the kernel.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Steve Wahl <steve.wahl@hpe.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com

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Mike Travis 2022-04-06 14:51:48 -05:00 • committed by Borislav Petkov

parent d812f7c475

commit bb3ab81bdb

1 changed files with 7 additions and 1 deletions

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arch/x86/kernel/apic/x2apic_uv_x.c

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