cxgb4: Update IngPad and IngPack values

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We are using the smallest padding boundary (8 bytes), which isn't
smaller than the Memory Controller Read/Write Size

We get best performance in 100G when the Packing Boundary is a multiple
of the Maximum Payload Size. Its related to inefficient chopping of DMA
packets by PCIe, that causes more overhead on bus. So driver is helping
by making the starting address alignment to be MPS size.

We will try to determine PCIE MaxPayloadSize capabiltiy  and set
IngPackBoundary based on this value. If cache line size is greater than
MPS or determinig MPS fails, we will use cache line size to determine
IngPackBoundary(as before).

Signed-off-by: Arjun Vynipadath <arjun@chelsio.com>
Signed-off-by: Casey Leedom <leedom@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Arjun Vynipadath 2017-03-20 14:22:38 +05:30 • committed by David S. Miller

parent 3588f29e06

commit bb58d07964

2 changed files with 60 additions and 19 deletions

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77

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

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4

drivers/net/ethernet/chelsio/cxgb4/t4_values.h

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