riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC

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Add clock generator node for CV1800B and CV1812H.

Until now, It uses DT override to minimize duplication. This may
change in the future. See the last link for the discussion on
maintaining DT of CV1800 series.

Link: 6f4e9b8ecb/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB4953ED6A4B57773865F49D6DBB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

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Inochi Amaoto 2024-03-09 17:02:55 +08:00

parent 89a7056ed4

commit bb7b341962

3 changed files with 14 additions and 0 deletions

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arch/riscv/boot/dts/sophgo/cv1800b.dtsi

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arch/riscv/boot/dts/sophgo/cv1812h.dtsi

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arch/riscv/boot/dts/sophgo/cv18xx.dtsi

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