powerpc/8xx: Don't use page table for linear memory space

Browse source

Instead of using the first level page table to define mappings for
the linear memory space, we can use direct mapping from the TLB
handling routines. This has several advantages:
* No need to read the tables at each TLB miss
* No issue in 16k pages mode where the 1st level table maps 64 Mbytes

The size of the available linear space is known at system startup.
In order to avoid data access at each TLB miss to know the memory
size, the TLB routine is patched at startup with the proper size

This patch provides a 10%-15% improvment of TLB miss handling for
kernel addresses

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>

...

This commit is contained in:

Christophe Leroy 2016-05-17 09:02:51 +02:00 • committed by Scott Wood

parent 6264dbb98f

commit bb7f380849

2 changed files with 55 additions and 72 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

71

arch/powerpc/kernel/head_8xx.S

View file

56

arch/powerpc/mm/8xx_mmu.c

View file