arm64: dts: qcom: sm6350: Set up DDR & L3 scaling

Browse source

Add the CPU OPP tables including core frequency and L3 bus frequency.
The L3 throughput values were chosen by studying the frequencies
available in HW LUT and picking the highest one that's less than the
CPU frequency. DDR clock rates come from the vendor kernel.

Available values from the HW LUT:
300000000
556800000
652800000
806400000
844800000
940800000
1132800000
1209600000
1286400000
1401600000
1459200000

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org

...

This commit is contained in:

Konrad Dybcio 2023-01-04 18:16:42 +01:00 • committed by Bjorn Andersson

parent e17a806571

commit bba952275b

2 changed files with 159 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

140

arch/arm64/boot/dts/qcom/sm6350.dtsi

View file

19

arch/arm64/boot/dts/qcom/sm7225.dtsi

View file