ARM: davinci: da8xx: fix interrupt handling

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CP_INTC code in entry-macro.S code reads SECR1n register to see if
an interrupt was indeed pending. This register is actually marked as
write-only in the OMAP-L138 TRM. Moreover, the code just checks to see
the entire register is non-zero and does not check a specific interrupt
number.

Fix this to use interrupt pending bit in GIPR register for this purpose.
GIPR register is already being read to know the highest priority interrupt
pending.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>

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This commit is contained in:

Sekhar Nori 2012-06-20 23:10:13 +05:30

parent 485802a6c5

commit bbb33445b9

1 changed files with 3 additions and 5 deletions

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arch/arm/mach-davinci/include/mach/entry-macro.S

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