powerpc/powernv: Implement multilevel TCE tables

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TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
on huge guests (hundreds of GB of RAM) so the kernel might be unable to
allocate contiguous chunk of physical memory to store the TCE table.

To address this, POWER8 CPU (actually, IODA2) supports multi-level
TCE tables, up to 5 levels which splits the table into a tree of
smaller subtables.

This adds multi-level TCE tables support to
pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages()
helpers.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

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Alexey Kardashevskiy 2015-06-05 16:35:19 +10:00 • committed by Michael Ellerman

parent 43cb60ab7f

commit bbb845c4ba

3 changed files with 111 additions and 9 deletions

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2

arch/powerpc/include/asm/iommu.h

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105

arch/powerpc/platforms/powernv/pci-ioda.c

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13

arch/powerpc/platforms/powernv/pci.c

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